View S5N8951_877122.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

S5N8951X
G.dmt ADSL Analog Front End IC
Preliminary Information (Revision 1.0) July 2000
SAMSUNG ELECTRONICS CONFIDENTIAL PROPRIETARY
Copyright (c)1999-2000 Samsung Electronics, Inc. All Rights Reserved
S5N8951X
G.dmt ADSL Analog Front End IC
Contents
Page
1 Overview...................................................................................... 3
1.1 General Description.............................................................. 3 1.2 Features ................................................................................. 3 1.3 Absolute Maximum Ratings.................................................. 4 1.4 Electrical Specifications........................................................ 4
2 Signal description ......................................................................... 6
2.1 Functional Block Diagram.................................................... 6 2.2 I/O Pins Descriptions ............................................................ 7 2.3 Pin Configurations ................................................................ 9
3 Block Description....................................................................... 10
3.1 ADC/DAC............................................................................ 10 3.2 Tx/Rx LPF........................................................................... 10 3.3 Tx/Rx AGC......................................................................... 10
4 Digital Signal Interface ...............................................................11
4.1 Command Signal Interface ..................................................11 4.2 Data Signal Interface .......................................................... 18 5 Application Circuit ...................................................................... 19 5.1 ATU-R ................................................................................. 19 5.2 ATU-C ................................................................................. 20 6 Package Information.................................................................... 21
CONFIDENTIAL
2
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
1. OVERVIEW This chapter provides an overview of the S5N8951X01 ADSL ATU-C & ATU-R Analog Front End Chip. 1.1 General Descriptions The S5N8951X01 is Analog Front End IC designed for DMT based universal ADSL(Asymmetric Digital Subscribe Line) modems with 0.35u fully CMOS technology. It has 25.875 ~ 138KHz Upstream channel and 142.312 ~ 1104KHz bandwidth Downstream channel. The S5N8951X01 includes AGC, LPF, ADC, DAC. The AGC has 42dB gain 0.4dB step in RX mode and -24dB gain 2dB step in TX mode with 12bit/8bit control bits. Anti alias LPF has 1104KHz passband frequency in RX path and 138KHz in TX path. Samsung' s ADSL AFE chip provides 14bit ADC at 4.416M or 8.832M sample rates and 14bit 4.416MHz, 8.832MHz DAC. An 10bit DAC support VCXO control for timing recovery. The VCXO is divided into a crystal driver at 35.328MHz. 1.2 Features
l l l l l l l l l l l l
Integrated Analog Front End(AFE) for ADSL ATU-C & ATU-R Complies with G.dmt and G.lite Up to 1104Kbit/s down stream and 138Kbit/s upstream channel 14bit 4.416MS/s or 8.832MS/s ADC 14bit 4.416MHz or 8.832MHz DAC 5th-order Low Pass anti-alias Filter TX/RX paths RX 42dB 0.4dB step gain range with 12bit control signal TX -24dB 2dB step gain range with 8bit control signal 10bit 4KHz VCXO DAC Fully 0.35um CMOS technology 3.3V Power supply operation 0.4W Power comsumption
CONFIDENTIAL
3
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
1.3 Absolute Maximum Ratings Symbol VDD VIN IIN TOPR TSTG Parameter DC Supply Voltage DC input Voltage 5V tolerant DC input Current Operation Temperature Storage Temperature Min -0.3 -0.3 -0.3 -10 -40 -40 Typ Max 3.8 VDD+0.3 5.5 10 85 125 Units V V V mA degree C degree C
1.4 Electrical Specifications Parameter Power Supply Power Consumption THD SNR AGC Gain Range AGC Step Size AGC Step Error AGC Input Range LPF Cut Off Frequency LPF Output Range LPF Pass Band Ripple LPF Stop Band Attenuation THD SNR AGC Gain Range AGC Step Size AGC Step Error AGC Output Range LPF Cut Off Frequency LPF Pass Band Ripple LPF Stop Band Attenuation LPF Input Range Min 3.0 Typ Max General 3.3 3.6 450 Rx Path 70 70 42 0.4 0.2 2 1104 2 0.5 TX Path 70 70 0 2 0.2 2 138 0.5 2 ADC Units V mW Notes/Conditions
Normal Operation
0
-0.5 60
dB dB dB Vppd KHz Vppd dB dB
12bit Control
5th Butterworth
at 4.416MHz
-24
-0.5 24
dB dB dB Vppd KHz dB dB Vppd
8bit Control
5th Chebyshev at 276KHz
CONFIDENTIAL
4
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
Resolution Effective Number Of Bits Sampling Rate Full Scale Input Range Resolution Effective Number Of Bits Sampling Rate Full Scale Output Range Resolution Sampling Rate Maximum Output Range Minimum Output Range 14 13 4.416 2.0 DAC 14 12 4.416 2.0 VCXO DAC 10 4 2.5 0.5 bits bits MHz Vppd bits bits MHz Vppd bits KHz V V
Selectable 8.832MHz
Selectable 8.832MHz
CONFIDENTIAL
5
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
2. SIGNAL DESCRIPTION 2.1 Functional Block Diagram
TX_OUTP TX_DATA [13:0]
14bit DAC
TX LPF
TX AGC
TX_OUTN
MCLK AUXCLK CONT_DAX
10bit DAC
CBG
SCLK SEN SDIN SDOUT RESETN
AUTO TUNNING CONTROL LOGIC & REGISTER
BANDGAP & VI REF
REXT
RX_INP RX_INN RX_DATA [13:0]
14bit ADC
RX LPF
RX AGC
RX_INPG RX_INNG
Figure 2.1.1 S5N8951X01 Functional Block Diagram
CONFIDENTIAL
6
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
2.2 I/O Pins Description
Signal Name
RESETN CS1 CS0 TM1 TM0 TX_DATA[13:0] MCLK AUXCLK TX_DACOP TX_DACON COMP_DAC IREF_DAC RX_DATA[13:0] RX_ADCIP RX_ADCIN BGR_ADC REFT_ADC REFB_ADC SCLK SEN SDOUT SDIN TX_OUTP TX_OUTN TX_FINP TX_FINN RX_INP RX_INN RX_INPG RX_INNG RX_FOUTP RX_FOUTN
Num
48 49 50 51 52 94~100, 1~7 8 11 90 89 88 87 12 ~ 25 28 29 32 33 34 44 45 46 47 78 77 85 86 58 57 56 55 31 30
Type
CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Analog Analog Analog Analog CMOS Analog Analog Analog Analog Analog CMOS CMOS CMOS CMOS Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog
I/O General Pins
I I I I I I I I O I I O I -
Description
System Reset. Active Low Chip Select Chip Select Digital Interface Selection "0" = 14bits , "1"=7bits*2 "0" = RT , "1" = CO
DAC Interface
DAC 14bit Data Inputs If TM1=1, TX_DATA[13:7] is invalid Master Clock 8.832MHz(Selectable 17.664MHz) In 7bits Data Interface mode, AUXCLK=MCLK/2 In 14bits Data Interface mode, pin is open or ground. DAC Current Positive Output for TX path DAC Current Negative Output for TX path Compensation Capacitor 0.1uF Connection for TX path External Resistor 1.24k Connection
ADC Interface
ADC 14bit Data Outputs ( If TM1=1, [13:7] is always low) ADC Positive Input ADC Negative Input ADC Band gap Reference Output ADC Top Reference Output ADC Bottom Reference Output
DSP Interface
Serial Data Clock Serial Data Enable Serial Data Output Serial Data Input Tx Analog Positive Output Tx Analog Positive Output Tx Filter Analog Positive Input Tx Filter Analog Negative Input Rx Analog Positive Input Rx Analog Negative Input Rx Analog External -14dB Gain Positive Input Rx Analog External -14dB Gain Negative Input Rx Filter Analog Positive Output Rx Filter Analog Negative Output
TX Pass Interface
RX Pass Interface
Voltage Reference
CONFIDENTIAL
7
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
TX_VCOM RX_VCOM CBG_REF REXT_REF CONT_DAX RX_AOUTP RX_AOUTN RX_FINN RX_FINP TX_AINP TX_AINN TX_FOUTN TX_FOUTP AVDD_DAC ASUB_DAC AVSS_DAC DVDD_DAC DVSS_DAC AVDD_DAX AVSS_DAX AVDD_ADC ASUB_ADC AVSS_ADC DVDD_ADC DVSS_ADC AVDD_TX AVSS_TX ASUB_TX AVDD_FAT AVSS_FAT AVDD_RX AVSS_RX ASUB_RX AVDD_REF AVSS_REF ASUB_REF DVDD_CTL DSUB_CTL DVSS_CTL 80 64 68 67 40 60 61 62 63 81 82 83 84 91 92 93 10 9 38 39 35 36 37 27 26 79 76 75 74 71 59 54 53 69 66 65 41 42 43 Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply TX Pass Common Mode Voltage Rx Pass Common Mode Voltage Bandgap Reference Compensation Capacitor 100pF Reference Current External Resistor 6.8K VCXO Control Voltage Output Rx AGC Analog Positive Output Rx AGC Analog Negative Output Rx Filter Analog Negative Input Rx Filter Analog Positive Input Tx AGC Analog Positive Input Tx AGC Analog Positive Input Tx Filter Analog Negative Output Tx Filter Analog Negative Output (Only RT)
VCXO Interface CO Pass (TM0 = "1")
Power Supply
Tx Analog DAC VDD Tx Analog DAC SUB Tx Analog DAC VSS Tx Digital DAC VDD Tx Digital DAC VSS VCXO DAC Analog VDD VCXO DAC Analog VSS Rx Analog ADC VDD Rx Analog ADC SUB Rx Analog ADC VSS Rx Digital ADC VDD Rx Digital ADC VSS Tx Path VDD Tx Path VSS TX Path SUB Filter Auto Tuning VDD Filter Auto Tuning VSS Rx Filter VDD Rx Filter VSS Rx Filter SUB Reference VDD Reference VSS Reference SUB Control Logic VDD Digital Substrate VSS Control Logic VSS
CONFIDENTIAL
8
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
2.3 Pin Configurations ( Top View)
TX_FOUTP
TX_DATA10
TX_DATA11
TX_DATA12
TX_DATA13
TX_DACON
TX_DATA7
TX_DATA8
TX_DATA9
ASUB_DAC
AVSS_DAC
TX_FOUTN
AVDD_DAC
TX_DACOP
COMP_DAC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
IREF_DAC
TX_AINN
TX_FINN
TX_AINP
TX_FINP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
TX_DATA6 TX_DATA5 TX_DATA4 TX_DATA3 TX_DATA2 TX_DATA1 TX_DATA0 MCLK DVSS_DAC DVDD_DAC AUX_CLK RX_DATA0 RX_DATA1 RX_DATA2 RX_DATA3 RX_DATA4 RX_DATA5 RX_DATA6 RX_DATA7 RX_DATA8 RX_DATA9 RX_DATA10 RX_DATA11 RX_DATA12 RX_DATA13 DVSS_ADC DVDD_ADC RX_ADCIP RX_ADCIN RX_FOUTN AVDD_ADC CONT_DAX ASUB_ADC AVDD_DAX
TX_VCOM AVDD_TX TX_OUTP TX_OUTN AVSS_TX ASUB_TX AVDD_FAT NC NC AVSS_FAT NC AVDD_REF CBG_REF
S5N8951X01
(100-QFP)
REXT_REF AVSS_REF ASUB_REF RX_VCOM RX_FINP RX_FINN RX_AOUTN RX_AOUTP AVDD_RX RX_INP RX_INN RX_INPG RX_INNG AVSS_RX ASUB_RX TM0 TM1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
REFB_ADC
DVDD_CTL
AVSS_ADC
RX_FOUTP
DSUB_CTL
REFT_ADC
AVSS_DAX
DVSS_CTL
BGR_ADC
RESETN
SDOUT
SCLK
SDIN
SEN
CS1
CONFIDENTIAL
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
9
Preliminary Information (Rev.1.0)
CS0
S5N8951X
G.dmt ADSL Analog Front End IC
3. BLOCK DESCRIPTIONS 3.1 ADC / DAC S5N8951X01 has a 14bit resolution ADC 4.416M/8.832M sample frequency. The input of ADC is fully differential 2.0Vppd Max. The ADC transforms the signal into a digital 14bit output. There are two type of DAC' s in S5N8951X01. One is for TX. It is 14bit 4.416MHz/8.832MHz frequency. Samsung' s DMT(S5N8950) transmit 14bit parallel data to the AFE chip. The other DAC is for VCXO control. It has 10bit resolution 4KHz frequency. Internal registers of S5N8951X01 transform 10bit VCXO control serial data from DSP into 10bit parallel data. And VCXO output analog signal CONT_DAX(Pin #40).
3.2 TX/RX LPF 3.2.1 RX FILTERS The combination of the external filter ( an LC ladder filter typically ) with the integrated low pass filter must provide: DMT sidelobe and out of band ( anti-aliasing ) attenuation Anti alias filter ( 60dB rejection @ image frequency ) On chip tuning circuit included.
3.2.2 TX FILTERS The TX Filters act not only to suppress the DMT sidebands but also as smoothing filters on the D/A converter' s output to suppress the image spectrum. For this reason they are realized in a time continuous approach and on chip tuning circuit included
3.3 TX/RX AGC TX AGC has 0~-24dB gains with 2dB step. It is controlled through 8bit serial digital signal from DSP. Internal registers of Samsung AFE Chips transform 8bit parallel control data. It outputs 2Vppd fully differential signal to line driver. RX AGC has low noise 0~42dB gains with 0.4dB step and It is controlled through 12bit + 1MSB control signal. If 1MSB is high, another RX input pass pin#55 RX_INNG #56 RX_INNP(external -14dB gain pass) is seclected. It inputs 2Vppd fully differential signal to RX LPF.
CONFIDENTIAL
10
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
4. DIGITAL SIGNAL INTERFACE 4.1 Command Signal Interface This description hold for ATU-R (S5N8951X01). The chip consists of four kinds of register map: - Power Control - Transmitter AGC - Receiver AGC - VCXO Control - Clock Selection Serial interfaces use three pins: - Clock - Serial data input(25-bit: 2bit cs + 5bit address + 1bit r/w + 16 bit data + 1bit dummy) - Serial data output(16 bit data) - Enable Serial Data Configuration Serial Data (SDAT)
R / W A 0 0 R / W R / W R / W R / W R / W R / W D 1 5 X D 1 4 X D 1 3 X D 1 2 X D 1 1 X D 1 0 X D 9 X D U M M Y D 6 P C 6 T A 6 R A 6 V C 6 X D 5 P C 5 T A 5 R A 5 V C 5 X D 4 P C 4 T A 4 R A 4 V C 4 X D 3 P C 3 T A 3 R A 3 V C 3 X D 2 P C 2 T A 2 R A 2 V C 2 X D 1 P C 1 T A 1 R A 1 V C 1 C K 1 D 0 P C 0 T A 0 R A 0 V C 0 C K 0 X
REGISTER
CS
ADDRESS
DATA
PWR_CTL
TX_AGC
C S 1 C S 1 C S 1 C S 1 C S 1 C S 1
C S 0 C S 0 C S 0 C S 0 C S 0 C S 0
A 4 X
A 3 X
A 2 0
A 1 0
D 8 X
D 7 P C 7 T A 7 R A 7 V C 7 X
X
X
X
0
0
1
X
X
X
X R A 1 2 X
X R A 1 1 X
X R A 1 0 X
X R A 9 V C 9 X
X R A 8 V C 8 X
X
RX_AGC
X
X
0
1
0
X
X
X
X
VCXO_CTL
X
X
0
1
1
X
X
X
X
CLK_SEL
X
X
1
0
0
X
X
X
X
X
X
X
X = Don' t care R/W =0 -> Read R/W =1 -> Write
CONFIDENTIAL
11
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
4.1.1 Register Map 4.1.1.1 Power Control The power on/off control of AFE blocks on this chip is set by the PWR_CTL register, (XX000), as described below: PWR_CTL Register (A4A3A2A1A0=XX000) DATA NAME RESET VALUE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0 0 0 0 0 0 0 0
Power Control is as follow. PC7 PC6 PC5 PC4 PC3 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0
PC2 0 0 0 1 0 0 0 0 0
PC1 0 0 1 0 0 0 0 0 0
PC0 0 1 0 0 0 0 0 0 0
HEX 0000 0001 0002 0004 0008 0010 0020 0040 0080
DESCRIPCION Normal Operation N/A N/A TX DAC Power Down TX Filter & AGC Power Down RX ADC Power Down Rx Filter Power Down Rx AGC Power Down VCXO DAC Power Down
Adding Power Down (based on upper power down) 0 0 0 1 1 0003 N/A 0 1 1 0 0 000C TX Path Power Down 1 0 0 0 0 0070 Rx Path Power Down 1 1 1 1 1 00FF Whole Chip Power Down
CONFIDENTIAL
12
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
4.1.1.2 Transmitter AGC The main functions of the TX path are controlled by the TX_AGC registers, as described below: TX_AGC Register (A4A3A2A1A0=XX001) DATA NAME RESET VALUE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 0 0 0 1 0 0 0 1
TA[7:0] TX path output attenuator gain setting. 0 to -24dB attenuation in 2 dB steps. (default is 0 dB).
TA[7] 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
TA[6] 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
TA[5] 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
TA[4] 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
TA[3] 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
TA[2] 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0
TA[1] 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
TA[0] 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
HEX 0011 0012 0014 0018 0021 0022 0024 0028 0041 0042 0044 0048 0081 0082 0084 0088
GAIN(dB) 0 -2 -4 -6 -6 -8 -10 -12 -12 -14 -16 -18 -18 -20 -22 -24
CONFIDENTIAL
13
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
4.1.1.3 Recieve AGC The main functions of the RX path are controlled by the RX_AGC register, as described below: RX_AGC Register (A4A3A2A1A0=XX010) DATA NAME RESET VALUE D15 D14 D13 D12 D11 D10 RA 12 0 RA 11 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RA RA9 RA8 RA7 RA6 RA4 RA4 RA3 RA2 RA1 RA0 10 0 0 0 1 0 0 1 0 0 0 0
RA[11:0]: Receive path input gain setting 0 to 42dB gain in 0.4 dB steps. (default is 0 dB). RA[12] is " 1" ,the external attenuation gain(ex, -14dB) path pin#55 RX_INNG #56 RX_INPG will be enable. RA[12] should only be utilized the short line conditions.
RA [12] RA [11] RA [10]
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
RA [9] 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
RA [8] 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
RA [7] 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
RA [6] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
RA [5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
RA [4] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
RA [3]
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
RA RA [2] [1] 0000 ~ 1111 0000 ~ 1111 0000 ~ 1111 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0000 ~ 1111 0000 ~ 1111 0000 ~ 1111 0000 ~ 1111 0000 ~ 1111 0000 ~ 1111
RA [0]
HEX 1090~109F 1110~111F 1210~121F 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 009A 009B 009C 009D 009E 009F 0110~011F 0210~021F 0410~041F 0810~081F 0820~082F 0840~084F
GAIN(dB) -14.0~-8.0 -8.0~-2.0 -2.0~4.0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 6.0~12.0 12.0~18.0 18.0~24.0 24.0~30.0 30.0~36.0 36.0~42.0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CONFIDENTIAL
14
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
4.1.1.4 VCXO Control The VCXO DAC is 10-bit voltage-mode DAC designed to be monotonic and intended to be operated at a 4 kHz update rate. In order to update the DAC, the user must write to the VCXO register through the serial port. The individual bit definitions are given below. VCXO_CTL Register (A4A3A2A1A0=XX011) DATA NAME RESET VALUE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VC9 VC8 VC7 VC6 VC4 VC4 VC3 VC2 VC1 VC0 1 0 0 0 0 0 0 0 0 0
VC[9:0]: VCXO DAC 10-bit word. The DAC nominal output voltages for extreme and mid-scale codes are as follows. VC[9:0] = 0000000000 = 0.5 V VC[9:0] = 1000000000 = 1.5 V (mid-range) VC[9:0] = 1111111111 = 2.5 V A general expression for the DAC output voltage is 0.5 V + (CODE / 1024) X (2.0 V) where CODE is the decimal integer value of the 10-bit word formed by VCXO[9:0].
CONFIDENTIAL
15
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
4.1.1.5 Clock Selection Main functions of Clock Selection are frequency selection of each MCLK/AUXCLK/ADC. The individual bit definitions are given below. CLK_SEL Register (A4A3A2A1A0=XX100) DATA NAME RESET VALUE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CK1 CK0 0 0
TM1, CK[1:0] : Clock Selection has eight possible clocking configuration as follow. TM1 2 Phase CK1 CK0 HEX MCLK AUXCLK DAC 0 OFF 0 0 0000 4.416 MHz 0 4.416 MHz 0 0 0 1 1 1 1 OFF OFF OFF ON ON ON ON 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0001 0002 0003 0000 0001 0002 0003 4.416 MHz 8.832MHz 8.832MHz 8.832MHz 8.832MHz 17.664MHz 17.664MHz 0 0 0 4.416 MHz 4.416 MHz 8.832MHz 8.832MHz 4.416 MHz 8.832MHz 8.832MHz 4.416 MHz 4.416 MHz 8.832MHz 8.832MHz
ADC 2.208 MHz 4.416 MHz 4.416 MHz 8.832MHz 4.416 MHz 2.204 MHz 8.832 MHz 4.416 MHz
CONFIDENTIAL
16
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
4.1.2 Serial Data Interface 4.1.2.1 Physical Interface Serial interfaces use three pins: - Clock - Serial data (25-bit: 2bit cs + 5bit address + 1bit r/w + 16 bit data + 1bit dummy) - Enable
S5N8950
AFE_SCLK AFE_SEN
S5N8951X01
(DM T)
AFE_SDOUT AFE_SDIN
(AFE)
4.1.2.2 Waveform
TPWL TSU1 TCYC TPWH TH2TSU2 TH1 TPW
SEN SCLK SDIN SDOUT
CS1 CS0 A4 A3 A2 A1 A0 R/W D15 TD3 D15 D14 D1 D0 D14 D1 D0
Dummy
TD4
Parameter SCLK Clock Period SCLK High Time SCLK Low Time SEN Low To SCLK High SCLK High To SEN High SEN Inactive Pulse Time SDIN Setup time SDIN Hold time SCLK low to SDOUT delay SEN inactive to SDOUT HiZ
Symbol TCYC TPWH TPWL TSU1 TH1 TPW TSU2 TH2 TD3 TD4
Min 452 452 30 15 905 15 15
Typ 905
Max
30 30
Unit nS nS nS nS nS nS nS nS nS nS
CONFIDENTIAL
17
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
4.2 Data Interface 4.2.1 Physical Interface l l l ADC and DAC data transmission between S5N8951X01 and S5N8950 Parallel Interface : 29 pin (14 ADC bit data, 14 DAC bit data, MCLK) Parallel Interface(S5N8950) : 16 pin (7 ADC bit data, 7 DAC bit data, MCLK,AUXCLK)
TX_DATA[6:0] MCLK
S5N8950
AU XCLK
S5N8951X01 (AFE)
RX_DATA[6:0]
(DMT)
4.2.2 Waveform
TCYC TD TPWH TPWL TD
MCLK
TX_DATA
TX_DATA[13:0]
TX_DATA[13:0]
TX_DATA[13:0] TSU
TX_DATA[13:0] TH
RX_DATA
RX_DATA[13:0]
RX_DATA[13:0]
Figure 4.2.1 Waveform of 14bit parallel interface (TM1=0)
TSU2 TD TH2
MCLK
AUXCLK
N-1
TX_DATA
TX_DATA[6:0]
N-1
TX_DATA[13:7]
N
TX_DATA[6:0]
N
TX_DATA13:7]
N-1
RX_DATA
RX_DATA[6:0]
N-1
RX_DATA[13:7]
N
RX_DATA[6:0]
N
RX_DATA[13:7]
Figure 4.2.2 Waveform of 7bit parallel interface (TM1=1)
Parameter MCLK Clock Period MCLK High Time MCLK Low Time DATA Delay after MCLK RX_DATA setup to MCLK RX_DATA hold to MCLK AUXCLK setup to MCLK AUXCLK hold to MCLK
Symbol TCYC TPWH TPWL TD TSU TH TSU2 TH2
Min
Typ 113 57 57
Max
10 15 42 10 10
Unit nS nS nS nS nS nS nS nS
Note MCLK=4.416MHz MCLK=4.416MHz MCLK=4.416MHz MCLK=4.416MHz MCLK=4.416MHz
CONFIDENTIAL
18
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC
5. Application Circuit 5.1 ATU-R
P1 P2 P3 P4 P8 P9 P10
10u
0.1u
10u
0.1u
10u
0.1u
10u
0.1u
0.0375k 0.0375k
0.1u 0.1u
1k 1k
10u
0.1u
10u
0.1u
10u
0.1u
G1
G2
G3
G4
G8
G9
G10
1.24k
0.1u G1
P1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83 TX_FOUTN
82 TX_AINN
ASUB_DAC
AVDD_DAC
COMP_DAC
TX_DATA10
TX_DATA11
TX_DATA12
TX_DATA13
AVSS_DAC
TX_DATA7
TX_DATA8
TX_DATA9
TX_DACOP
TX_DACON
IREF_DAC
TX_FOUTP
TX_FINN
TX_FINP
TX_AINP
81
1u
TX_VCOM AVDD_TX TX_OUTP TX_OUTN AVSS_TX ASUB_TX AVDD_FAT NC 80 79 78 77
1 2
TX_DATA6 TX_DATA5 TX_DATA4 TX_DATA3 TX_DATA2 TX_DATA1 TX_DATA0 MCLK DVSS_DAC
39n
P10
DA<6:0>
3 4 5 6 7
TX_OUTP 39n TX_OUTN 5.1k
76 75 74 73 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 72
MCLK G2 P2
8 9
G10 P9
5.1k
S5N8950 Interface
AVSS_FAT
P9
AUXCLK
11
AUXCLK NC AVDD_REF
P8
100p 6.8k
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
RX_DATA0 RX_DATA1 RX_DATA2 RX_DATA3 RX_DATA4 RX_DATA5 RX_DATA6 RX_DATA7 RX_DATA8 RX_DATA9 RX_DATA10 RX_DATA11 RX_DATA12 RX_DATA13 DVSS_ADC DVDD_ADC RX_ADCIP RX_ADCIN RX_FOUTN
AD<6:0>
S5N8951X01 (100QFP)
CBG_REF REXT_REF AVSS_REF ASUB_REF RX_VCOM RX_FINP RX_FINN RX_AOUTN RX_AOUTP AVDD_RX RX_INP RX_INN RX_INPG RX_INNG AVSS_RX ASUB_RX TM0
G8
1u
1k 1k 1k 1k 39n RX_INP 39n RX_INN 39n G7 4.3k 39n 4.3k
P7
G3 P3
AVDD_ADC
CONT_DAX
ASUB_ADC
REFB_ADC
DVDD_CTL
AVSS_ADC
RX_FOUTP
DSUB_CTL
REFT_ADC
AVSS_DAX
AVDD_DAX
DVSS_CTL
BGR_ADC
0.1u
0.1u
RESETN
TM1 CS1 CS0
SDOUT
SCLK
SDIN
SEN
P6
G6
31
32
33
35
36
37
38
39
34
40
41
42
43
44
45
46
47
48
P4 10u 0.1u 10u 0.1u 10u 0.1u
P5 G5
P6
G6
P5 P6 P7
49
50
10u G4
0.1u
10u
0.1u
10u
0.1u
G5
G6
G7
SCLK SEN SDOUT SDIN RESETN VCXO CS1 CS0
System Interface
CONFIDENTIAL
19
Preliminary Information (Rev.1.0)
Line Interface
10
DVDD_DAC
NC
S5N8951X
G.dmt ADSL Analog Front End IC
5.2 ATU-C
P1 P2 P3 P4 P8 P9 P10
10u
0.1u
10u
0.1u
10u
0.1u
10u
0.1u
0.0375k 0.0375k
0.1u 0.1u
1k 1k
10u
0.1u
10u
0.1u
10u
0.1u
G1
G2
G3
G4
G8
G9
G10
1.24k J2 J1 P1 J6 J5 J7 J8 J4 J3
0.1u G1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83 TX_FOUTN
82 TX_AINN
AVDD_DAC
TX_DATA10
TX_DATA11
TX_DATA12
TX_DATA13
ASUB_DAC
COMP_DAC
TX_DATA7
TX_DATA8
TX_DATA9
TX_DACOP
TX_DACON
AVSS_DAC
IREF_DAC
TX_FINN
TX_FINP
TX_FOUTP
TX_AINP
81
1u
TX_VCOM AVDD_TX TX_OUTP TX_OUTN AVSS_TX ASUB_TX AVDD_FAT NC 80 79 78 77
1 2
TX_DATA6 TX_DATA5 TX_DATA4 TX_DATA3 TX_DATA2 TX_DATA1 TX_DATA0 MCLK DVSS_DAC
39n
P10
DA<6:0>
3 4 5 6 7
TX_OUTP 39n TX_OUTN 5.1k 5.1k
76 75 74 73 71 72
MCLK G2 P2
8 9
G10 P9
AVSS_FAT
S5N8950 Interface
AUXCLK
11
AUXCLK NC AVDD_REF 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
G9
P8
100p 6.8k
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
RX_DATA0 RX_DATA1 RX_DATA2 RX_DATA3 RX_DATA4 RX_DATA5 RX_DATA6 RX_DATA7 RX_DATA8 RX_DATA9 RX_DATA10 RX_DATA11 RX_DATA12 RX_DATA13 DVSS_ADC DVDD_ADC RX_ADCIP RX_ADCIN RX_FOUTN
AD<6:0>
S5N8951X01 (100QFP)
CBG_REF REXT_REF AVSS_REF ASUB_REF RX_VCOM RX_FINP RX_FINN RX_AOUTN RX_AOUTP AVDD_RX RX_INP RX_INN RX_INPG RX_INNG AVSS_RX ASUB_RX
G8
1u
J1 J2 J6 J5 P7
1k 1k 1k 1k 39n RX_INP 39n RX_INN 39n
G3 P3
G7
4.3k 39n 4.3k P6
AVDD_ADC
CONT_DAX
ASUB_ADC
REFB_ADC
DVDD_CTL
AVSS_ADC
RX_FOUTP
DSUB_CTL
REFT_ADC
AVSS_DAX
AVDD_DAX
DVSS_CTL
BGR_ADC
0.1u J7 J4 J3 J8
0.1u
TM0 RESETN TM1 CS1 CS0 SDOUT
SCLK
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
SDIN
SEN
48
49
P4 10u 0.1u 10u 0.1u 10u 0.1u
P5G5
P6
G6
P5 P6 P7
50
10u G4
0.1u
10u
0.1u
10u
0.1u
G5
G6
G7
SCLK SEN SDOUT SDIN RESETN VCXO CS1 CS0
System Interface
CONFIDENTIAL
20
Preliminary Information (Rev.1.0)
Line Interface
10
DVDD_DAC
NC
S5N8951X
G.dmt ADSL Analog Front End IC
6. Package Information (100QFP-1420C)
CONFIDENTIAL
21
Preliminary Information (Rev.1.0)
S5N8951X
G.dmt ADSL Analog Front End IC Revision History
Revision No. 1.0 Date 2000-07-20 Description S5N8951X (Rev.1) Released.
IMPORTANT NOTICE
The information furnished by Samsung Electronics in this document is belived to be accurate and reliable. However, no resposibility is assumed by Samsung Electronics for its use, nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Samsung Electronics. Samsung Electronics reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete.
For More Information Tel: (82)-(31)-209-8301, Fax: (82)-(31)-209-8309 E-mail: kimil@sec.samsung.com http://www.intl.samsungsemi.com
Copyright (c)2000 Samsung Electronics, Inc. All Rights Reserved
CONFIDENTIAL
22
Preliminary Information (Rev.1.0)

▲Up To Search▲

Price & Availability of S5N8951

	To Download S5N8951 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .